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? 1999 microchip technology inc. ds30190h-page 1 pic16c5xx this document includes the programming specifications for the following devices: introduction overview the pic16c5x series is a family of single-chip cmos microcontrollers with on-chip eprom for program stor- age. the programming specification also applies to rom products for verification only. due to the special architecture of these microcontrol- lers (12-bit wide instruction word) and the low pin counts (starting at 18 pins), the eprom programming methodology is different from that of standard (byte- wide) eproms (e.g., 27c256). the pic16c5x series can be programmed by applying the 12-bit wide data word to the 12 available i/o pins while the address is generated by the on-chip program counter. the mclr /v pp pin provides the programming supply voltage (v pp ). programming/verify chip enable is controlled by the t0cki pin while the osc1 pin con- trols the program counter. this document describes all the programming details of the pic16c5x series and the requirements for pro- gramming equipment to be used from programming prototypes in the engineering lab up to high volume programming on the factory floor. pin diagrams pin descriptions (during programming): pic16c52/54/54a/54b/55/56/57/58a/58b ? pic16c52 ? pic16c55 ? pic16c57 ? pic16c54 ? pic16c55a ? pic16c57c ? pic16c54a ? pic16c56 ? pic16cr57b ? pic16c54b ? pic16c56a ? pic16cr57c ? pic16c54c ? pic16cr56a ? pic16c58a ? pic16cr54a ? pic16c58b ? pic16cr54b ? pic16cr58a ? pic16cr54c ? pic16cr58b mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 t0cki v dd nc v ss nc ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 ?1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c55 pic16c57/cr57b pdip, soic, windowed cerdip pdip, soic, windowed cerdip ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss rb0 rb1 rb2 rb3 ?1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pic16c54/54a/cr54a pic16c56 pic16c58a/cr58a pic16c52 pic16c58b/cr58b pin name during programming pin name pin type pin description t0cki prog/ver i program pulse input/verify pulse input ra0 - ra3 d0 - d3 i/o data input/output rb0 - rb7 d4 - d11 i/o data input/output osc1 incpc i increment program counter input mclr /v pp v pp p programming power v dd v dd p power supply v ss v ss p ground legend: i = input, o = output, p = power eprom/rom memory programming/verify specification
pic16c5xx ds30190h-page 2 ? 1999 microchip technology inc. 1.0 program/verify modes the pic16c5x series uses the internal program counter (pc) to generate the eprom address. v pp is supplied through the mclr pin. the t0cki pin acts as chip enable, alternating between programming and verifying. the osc1 pin is used for incrementing the pc. data is applied to, or can be read on porta and portb (msb on rb7, lsb on ra0). the programming/verify mode is entered by raising the level on the mclr pin from v il to v hh (= v pp ) while the t0cki pin is held at v ih and the osc1 pin is held at v il . the program counter now has the value 0xfff, because mclr was at v il before. this condition selects the configuration word as the very first eprom location to be accessed after entering the program/ver- ify mode. since the mclr pin was initially at v il , the device is in the reset state (the i/o pins are in the reset state). incrementing the pc once (by pulsing the osc1 pin) selects location 0x000 of the user program memory. afterwards all other memory locations from 001h through end of memory can be addressed by incre- menting the pc. if the program counter has reached the last address of the user memory area (e.g. 0x1ff for the pic16c54), and is incremented again, the on-chip special eprom area will be addressed. (see figure 1-2 to determine where the special eprom area is located for the vari- ous pic16c5x devices). 1.1 program/verify without pc increment after entering the program/verify mode, pulsing the t0cki pin low programs the data present on porta and portb into the memory location selected by the program counter. the duration of the t0cki low time determines the length of the programming pulse. pulsing the t0cki pin low again without changing the signals on mclr and osc1 puts the contents of the selected memory location out on porta and portb for verification of a successful programming cycle. this verification pulse on t0cki can be much shorter than the programming pulse. if the programming was not successful, t0cki can be pulsed low again to apply another programming pulse, followed again by a shorter t0cki low pulse for another verification cycle. this sequence can be repeated as many times as required until the programming is successful. 1.2 verify with pc increment if a verification cycle shows that programming was suc- cessful, the program counter can be incremented by keeping the t0cki input at a high level while pulsing the osc1 input high. when both t0cki and osc1 are high, the contents of the selected memory loca- tion is put out on ports a and b (= verify). the falling edge of osc1 will increment the program counter. a fast verify- only with automatic increment of the pc can be performed by entering the program/verify mode as described above and then clocking the osc1 input. if osc1 is high, the selected memory location is output on ports a and b, while the falling edge of osc1 will increment the program counter. thus, the first memory location to be verified after entering the program/verify mode, is the configuration word. the next location is 000h followed by 001h and so on. the program memory location n can be reached by gen- erating n + 1 falling edges on osc1. when osc1 is brought high again, the contents of address n are output on ports a and b as long as osc1 stays high. 1.3 programming/verifying configuration word the configuration word is logically mapped at program memory location 0xfff. the pc points to the config- uration word after mclr pin goes from low to v hh (high). the configuration word can be programmed or verified using the techniques described in section 1.1 and section 1.2. if pc is incremented, the next location it will point to is 0x000 in user memory. incrementing pc 4096 times will not allow the user to point to the configuration word. the only way to point to it again is to reset and re-enter program mode.
? 1999 microchip technology inc. ds30190h-page 3 pic16c5xx 1.4 programming method the programming technique is described in the follow- ing section. it is designed to guarantee good program- ming margins. it does, however, require a variable power supply for v cc . 1.4.1 programming method details essentially, this technique includes the following steps: 1. perform blank check at v dd = v dd min. report failure. the device may not be properly erased. 2. program location with pulses and verify after each pulse at v dd = v ddp : where v ddp = v dd range required during pro- gramming (4.75v - 5.25v). a) programming condition: v pp = 13.0v to 13.25v v dd = v ddp = 4.75v - 5.25v v pp must be 3 v dd + 7.25v to keep programming mode active. b) verify condition: v dd = v ddp v pp 3 v dd + 7.5v but not to exceed 13.25v if location fails to program after n pulses, (sug- gested maximum program pulses of 8) then report error as a programming failure. 3. once location passes step 2", apply 11x over- programming, i.e., apply eleven times the num- ber of pulses that were required to program the location. this will guarantee a solid program- ming margin. the overprogramming should be made software programmable for easy updates. 4. program all locations. 5. verify all locations (using speed verify mode) at v dd = v dd min 6. verify all locations at v dd = v dd max v dd min is the minimum operating voltage spec. for the part. v dd max is the maximum operating volt- age spec. for the part. 1.4.2 system requirements clearly, to implement this technique, the most stringent requirements will be that of the power supplies: v pp :v pp can be a fixed 13.0v to 13.25v supply. it must not exceed 14.0v to avoid damage to the pin and should be current limited to approximately 100ma. v dd : 2.0v to 6.5v with 0.25v granularity. since this method calls for verification at different v dd values, a programmable v dd power supply is needed. current requirement :100ma maximum microchip may release pic16c5xs in the future with different v dd ranges which make it necessary to have a programmable v dd . it is important to verify an eprom at the voltages specified in this method to remain consistent with microchip's test screening. for example, a pic16c5x specified for 4.75v - 5.25v should be tested for proper programming from 4.75v - 5.25v. 1.4.3 software requirements certain parameters should be programmable (and therefore easily modified) for easy upgrade. a) pulse width b) maximum number of pulses, current limit 8. c) number of over-programming pulses: should be = (a ? n) + b, where n = number of pulses required in regular programming. in our current algorithm a = 11, b = 0. 1.5 programming pulse width program memory cells : when programming one word of eprom, a programming pulse width (t pw ) of 100 m s is recommended. the maximum number of programming attempts should be limited to 8 per word. after the first successful verify, the same location should be over-programmed with 11x over-program- ming. configuration word :the configuration word for oscil- lator selection, wdt (watchdog timer) disable and code protection, requires a programming pulse width (t pwf ) of 10 ms. a series of 100 m s pulses is preferred over a single 10 ms pulse. note: device must be verified at minimum and maximum specified operating voltages as specified in the data sheet. note: any programmer not meeting the program- mable v dd requirement and the verify at v dd max and v dd min requirement may only be classified as prototype or devel- opment programmer but not a production programmer.
pic16c5xx ds30190h-page 4 ? 1999 microchip technology inc. figure 1-1: programming method flowchart n > 8? start blank check @ v dd = v dd min pass? report possible erase failure continue programming at users option program 1 location @ v pp = 13.0v to 13.25v v dd = v ddp n = n + 1 (n = # of program pulses) report programming failure increment pc to point to next location, n = 0 apply 11n additional program pulses pass? all locations done? verify all locations @ v dd = v dd min pass? report verify failure @ v dd min v dd = v dd max. verify all locations @ v dd = v dd max pass? report verify failure @ v dd max done ye s no ye s no no ye s no ye s ye s ye s no no now program configuration word verify configuration word @ v dd max & v dd min
? 1999 microchip technology inc. ds30190h-page 5 pic16c5xx figure 1-2: pic16c5x series program memory map in program/verify mode 1.6 special memory locations the id locations area is only enabled if the device is in a test or programming/verify mode. thus, in normal operation mode only the memory location 0x000 to 0xnnn will be accessed and the program counter will just roll over from address 0xnnn to 0x000 when incre- mented. the configuration word can only be accessed immedi- ately after mclr going from v il to v hh . the program counter will be set to all '1's upon mclr =v il . thus, it has the value 0xfff when accessing the configura- tion eprom. incrementing the program counter once by pulsing osc1 causes the program counter to roll over to all '0's. incrementing the program counter 4k times after reset (mclr = v il ) does not allow access to the configuration eprom. 1.6.1 customer id code locations per definition, the first four words (address ttt to ttt + 3) are reserved for customer use. it is recommended that the customer use only the four lower order bits (bits 0 through 3) of each word and filling the eight higher order bits with '0's. a user may want to store an identification code (id) in the id locations and still be able to read this code after the code protection bit was programmed. this is pos- sible if the id code is only four bits long per memory location, is located in the least significant nibble bound- ary of the 12-bit word, and the remaining eight bits are all '0's. example 1: customer code 0xd1e2 the customer id code 0xd1e2 should be stored in the id locations 200-203 like this: 200: 0000 0000 1101 201: 0000 0000 0001 202: 0000 0000 1110 203: 0000 0000 0010 reading these four memory locations, even with the code protection bit programmed would still output on port a the bit sequence 1101, 0001, 1110, 0010 which is 0xd1e2. address (hex) 000 bit number 11 0 nnn ttt ttt + 1 ttt + 2 ttt + 3 ttt + 3f (fff) for customer use (4 x 4 bit usable) for factory use configuration word 4 bit 0 0 id0 0 0 id1 0 0 id2 0 0 id3 user program memory (nnn + 1) x 12 bit nnn highest normal eprom memory address. nnn = 0x1ff for pic16c54, 54a, 55. nnn = 0x3ff for pic16c56 and 0x7ff for pic16c57, 58a. ttt start address of special eprom area and id locations. note: microchip will assign a unique pattern number for qtp and sqtp requests and for rom devices. this pattern number will be unique and traceable to the submitted code.
pic16c5xx ds30190h-page 6 ? 1999 microchip technology inc. 2.0 configuration word the configuration word is the very first memory location which is accessed after entering the program/verify mode of the pic16c5x. it contains the two bits for the selection of the oscillator type, the watchdog timer enable bit, and the code protection bit. all other bits (4 through 11) are read as '1's. one-time-programmable (otp) devices may have the oscillator configuration bits fosc0 and fosc1 set by the factory and are tested accordingly. therefore, it is essential that the inputs ra0 and ra1 are held at '1's when programming the wdte and/or the cp bit of the configuration word. otherwise, the factory tested and selected oscillator configuration could be overwrit- ten and the functionality of the device is not guaranteed any more. figure 2-1: configuration word for pic16cr54a/c54b/cr54b/c54c/cr54c/c55a/c56a/ cr56a/c57c/cr57b/cr57c/c58b/cr58a/cr58b figure 2-2: configuration word for pic16c52/c54/c54a/c55/c56/c57/c58a cp cp cp cp cp cp cp cp cp wdte fosc1 fosc0 register: config address: fffh bit1110987654321 bit0 bit 11-3: cp: code protection bits 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator cp wdte fosc1 fosc0 register: config address: fffh bit1110987654321 bit0 bit 11-4: unimplemented: read as 0 bit 3: cp: code protection bit. 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit (not implemented on pic16c52) 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits (2) 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note: pic16c52 supports xt and rc oscillator only. pic16lv54a supports xt, rc and lp oscillator only. pic16lv58a supports xt, rc and lp oscillator only.
? 1999 microchip technology inc. ds30190h-page 7 pic16c5xx 3.0 code protection the program code written into the eprom can be pro- tected by writing to the cp bit of the configuration word. all memory locations starting at 0x40 and above are protected against programming. it is still possible to program locations 0x00 through 0x3f, the id locations, and the configuration word. 3.1 programming locations 0 x 000 to 0 x 03f after code protection in a code protected part, these locations will program with the exception of the pic16crxx devices. they will read back scrambled data, with the exception of pic16cr54a and pic16cr58a. in any event, the pro- grammer cannot verify the device once it is code pro- tected. in code protected parts, the contents of the program memory cannot be read out in a way that the program code can be reconstructed. a location when read out will read as: 0000 0000 xxxx where xxxx is the xor of the three nibbles. for example, if the memory location contains 0xc04 (movlw 4), after code protection the output will be 0x008. in addition, all memory locations starting at 0x40 and above are protected against programming. it is still possible to program locations 0x000 through 0x03f and the configuration word. however, performing a ver- ify with activated code protection logic puts a 4-bit wide checksum on porta while the 8-bits of portb are read as '0's. the checksum is computed as follows: the four high order bits of an instruction word are xored with the four middle and the four low order bits, and the result is transferred to porta. all mem- ory locations are affected. to program location 0x000 to 0x03f in a code pro- tected part, the programmer should program one nibble at a time and verify the result through the xored out- put. for example, to program a location with 0xa93, first program the location with 0xff3, verify checksum to be 0x003; then program the location with 0xf93 and verify the xored output to be 0x00c and finally pro- gram the location with 0xa93 and verify the read-out to be 0x006. 3.2 embedding configuration word and id information in the hex file table 3-1: configuration word pic16c52 (cp enable pattern: xxxxxxxx0xxx) pic16c54 (cp enable pattern: xxxxxxxx0xxx) note: locations [0x000 : 0x03f] are not secure after code protection. to allow portability of code, a pic16c5x programmer is required to read the configuration word and id locations from the hex file when loading the hex file. if configuration word information was not present in the hex file then a simple warning message may be issued. similarly, while saving a hex file, all configuration word and id information must be included. configuration word should have the address of 0xfff. id locations are mapped at addresses described in section 1.6.1 and table 3-1. an option to not include this information may be provided. microchip technology inc. feels strongly that this feature is important for the benefit of the end customer. program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x17f] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled
pic16c5xx ds30190h-page 8 ? 1999 microchip technology inc. pic16c54a (cp enable pattern: xxxxxxxx0xxx) pic16cr54a (cp enable pattern: 000000000xxx) pic16c54b (cp enable pattern: 000000000xxx) pic16cr54b (cp enable pattern: 000000000xxx) pic16c54c (cp enable pattern: 000000000xxx) pic16cr54c (cp enable pattern: 000000000xxx) program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled read unscrambled id words [0x800 : 0x803] read unscrambled read unscrambled [0x040 : 0x7ff] read disabled read unscrambled [0x000 : 0x03f] read unscrambled read unscrambled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read unscrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read 0s, write disabled read unscrambled, write enabled [0x000 : 0x03f] read unscrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled read unscrambled id words [0x800 : 0x803] read unscrambled read unscrambled [0x040 : 0x7ff] read 0s read unscrambled [0x000 : 0x03f] read unscrambled read unscrambled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read unscrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read 0s write disabled read unscrambled, write enabled [0x000 : 0x03f] read unscrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled read unscrambled id words [0x800 : 0x803] read unscrambled read unscrambled [0x040 : 0x7ff] read 0s read unscrambled [0x000 : 0x03f] read unscrambled read unscrambled
? 1999 microchip technology inc. ds30190h-page 9 pic16c5xx pic16c55 (cp enable pattern: 000000000xxx) pic16c55a (cp enable pattern: 000000000xxx) pic16c56 (cp enable pattern: xxxxxxxx0xxx) pic16c56a (cp enable pattern: 000000000xxx) pic16cr56a (cp enable pattern: 000000000xxx) pic16c57 (cp enable pattern: xxxxxxxx0xxx) pic16c57c (cp enable pattern: 000000000xxx) program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x200 : 0x203] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x1ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x400 : 0x403] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x3ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x400 : 0x403] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x3ff] read 0s read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x400 : 0x403] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x3ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled
pic16c5xx ds30190h-page 10 ? 1999 microchip technology inc. pic16cr57b (cp enable pattern: 000000000xxx) pic16cr57c (cp enable pattern: 000000000xxx) pic16c58a (cp enable pattern: xxxxxxxx0xxx) pic16cr58a (cp enable pattern: 000000000xxx) pic16c58b (cp enable pattern: 000000000xxx) pic16cr58b (cp enable pattern: 000000000xxx) legend: x = dont care program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read scrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read scrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read scrambled, write disabled read unscrambled, write enabled [0x000 : 0x03f] read scrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled read unscrambled id words [0x800 : 0x803] read unscrambled read unscrambled [0x040 : 0x7ff] read disabled read unscrambled [0x000 : 0x03f] read unscrambled read unscrambled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled, write enabled read unscrambled, write enabled id words [0x800 : 0x803] read unscrambled, write enabled read unscrambled, write enabled [0x040 : 0x7ff] read 0s, write disabled read unscrambled, write enabled [0x000 : 0x03f] read unscrambled, write enabled read unscrambled, write enabled program memory segment r/w in protected mode r/w in unprotected mode configuration word (0xfff) read unscrambled read unscrambled id words [0x800 : 0x803] read unscrambled read unscrambled [0x040 : 0x7ff] read 0s read unscrambled [0x000 : 0x03f] read unscrambled read unscrambled
? 1999 microchip technology inc. ds30190h-page 11 pic16c5xx 3.3 checksum 3.3.1 checksum calculations checksum is calculated by reading the contents of the pic16c5x memory locations and adding up the opcodes up to the maximum user addressable location, e.g., 0x1ff for the pic16c54/55. any carry bits exceeding 16-bits are neglected. finally, the configura- tion word (appropriately masked) is added to the checksum. checksum computation for each member of the pic16c5x devices is shown in table . the checksum is calculated by summing the following: ? the contents of all program memory locations ? the configuration word, appropriately masked ? masked id locations (when applicable) the least significant 16 bits of this sum is the check- sum. the following table describes how to calculate the checksum for each device. note that the checksum cal- culation differs depending on the code protect setting. since the program memory locations read out differ- ently depending on the code protect setting, the table describes how to manipulate the actual program mem- ory values to simulate the values that would be read from a protected device. when calculating a checksum by reading a device, the entire program memory can simply be read and summed. the configuration word and id locations can always be read. note that some older devices have an additional value added in the checksum. this is to maintain compatibil- ity with older device programmer checksums. table 3-1: checksum computation device code protect checksum* blank value 0x723 at 0 and max address pic16c52 off on sum[0x000:0x17f] + cfgw & 0x00b sum_xor4[0x000:0x17f] + cfgw & 0x00b 0xfe8b 0x1683 0xecd3 0x1671 pic16c54 off on sum[0x000:0x1ff] + cfgw & 0x00f + 0x0ff0 sum_xor4[0x000:0x1ff] + cfgw & 0x00f 0x0dff 0x1e07 0xfc47 0x1df5 pic16c54a off on sum[0x000:0x1ff] + cfgw & 0xfff sum_xor4[0x000:0x1ff] + cfgw & 0x00f 0x0dff 0x1e07 0xfc47 0x1df5 pic16c54b off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x00:0x3f] + cfgw & 0xfff + sum_1d 0x0dff 0x0dc6 0xfc47 0xf332 pic16c54c off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x00:0x3f] + cfgw & 0xfff + sum_1d 0x0dff 0x0dc6 0xfc47 0xf332 pic16cr54a off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x00:0x3f] + cfgw & 0xfff + sum_1d 0x0dff 0x0dc6 0xfc47 0xf332 pic16cr54b off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x00:0x3f] + cfgw & 0xfff + sum_1d 0x0dff 0x0dc6 0xfc47 0xf332 pic16cr54c off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x00:0x3f] + cfgw & 0xfff + sum_1d 0x0dff 0x0dc6 0xfc47 0xf332 pic16c55 off on sum[0x000:0x1ff] + cfgw & 0x00f + 0x0ff0 sum_xor4[0x000:0x1ff] + cfgw & 0x00f 0x0dff 0x1e07 0xfc47 0x1df5 pic16c55a off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x000:0x3f] + cfgw & 0xfff + sum_id 0x0dff 0x0dc6 0xfc47 0xf322 pic16c56 off on sum[0x000:0x3ff] + cfgw & 0x00f + 0x0ff0 sum_xor4[0x000:0x3ff] + cfgw & 0x00f 0x0bff 0x3c07 0xfa47 0x3bf5 pic16c56a off on sum[0x000:0x3ff] + cfgw & 0xfff sum_xor4[0x000:0x3f] + cfgw & 0x00f + sum_id 0x0bff 0x0bc6 0xfa47 0xf132 legend: cfgw = configuration word sum[a:b] = sum of locations a through b inclusive sum_xor4[a:b] = xor of the four high order bits with the four middle and the four low of memory location order bits summed over the locations a through b inclusive. for example, location_a = 0x123 and location_b = 0x456, then sum_xor [location_a : location_b] = 0x0007. sum_id = id locations masked by 0xf then made into a 16-bit value with id0 as the most significant nibble. for example, id0 = 0x1, id1 = 0x2, id3 = 0x3, id4 = 0x4, then sum_id = 0x1234. *checksum = sum of all individual expressions modulo [0xffff] + = addition & = bitwise and
pic16c5xx ds30190h-page 12 ? 1999 microchip technology inc. pic16cr56a off on sum[0x000:0x1ff] + cfgw & 0xfff sum[0x000:0x3f] + cfgw & 0xfff + sum_id 0x0bff 0x0bc6 0xfa47 0xf132 pic16c57 off on sum[0x000:0x7ff] + cfgw & 0x00f + 0x0ff0 sum_xor4[0x000:0x7ff] + cfgw & 0x00f 0x07ff 0x7807 0xf647 0x77f5 pic16c57c off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x000:0x3f] + cfgw & 0xfff + sum_id 0x07ff 0x07c6 0xf647 0xed32 pic16cr57a off on sum[0x000:0x7ff] + cfgw & 0x00f + ff0 sum_xor4[0x00:0x7ff] + cfgw & 0xf 0x07ff 0x7807 0xf647 0x77f5 pic16cr57b off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x00x:0x3f] + cfgw & 0xfff + sum_id 0x07ff 0x07c6 0xf647 0xed32 pic16cr57c off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x00x:0x3f] + cfgw & 0xfff + sum_id 0x07ff 0x07c6 0xf647 0xed32 pic16c58a off on sum[0x000:0x7ff] + cfgw & 0x00f + 0x0ff0 sum_xor4[0x000:0x7ff] + cfgw & 0x00f 0x07ff 0x7807 0xf647 0x77f5 pic16c58b off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x000:0x7ff] + cfgw & 0xfff + sum_id 0x07ff 0x7c6 0xf647 0xed32 pic16cr58a off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x000:0x3f] + cfgw & 0xfff + sum_id 0x07ff 0x07c6 0xf647 0xed32 pic16cr58b off on sum[0x000:0x7ff] + cfgw & 0xfff sum[0x000:0x3f] + cfgw & 0xfff + sum_id 0x07ff 0x07c6 0xf647 0xed32 table 3-1: checksum computation (continued) device code protect checksum* blank value 0x723 at 0 and max address legend: cfgw = configuration word sum[a:b] = sum of locations a through b inclusive sum_xor4[a:b] = xor of the four high order bits with the four middle and the four low of memory location order bits summed over the locations a through b inclusive. for example, location_a = 0x123 and location_b = 0x456, then sum_xor [location_a : location_b] = 0x0007. sum_id = id locations masked by 0xf then made into a 16-bit value with id0 as the most significant nibble. for example, id0 = 0x1, id1 = 0x2, id3 = 0x3, id4 = 0x4, then sum_id = 0x1234. *checksum = sum of all individual expressions modulo [0xffff] + = addition & = bitwise and
? 1999 microchip technology inc. ds30190h-page 13 pic16c5xx 4.0 program/verify mode electrical characteristics 4.1 dc program characteristics) 4.2 ac program and test mode characteristics ) table 4-1: dc characteristics (ta = +10 c to +40 c) (25 c is recommended parameter no. symbol characteristics min. typ. max. units conditions pd1 v ddp supply voltage during pro- gramming 4.75 5.0 5.25 v note 1 pd2 i ddp supply current (from v dd )25.0mav dd = 5.0v, fosc1 = 5mhz pd3 v ddv supply voltage during verify v dd min v dd max pd5 v hh 2 voltage on mclr during pro- gramming 12.5 13.5 v pd6 i hh supply current from program- ming voltage source 100 ma pd7 i hh 2 current into mclr pin during programming (t0cki=0) 10.0 25.0 ma v hh = 13.5v, v dd = 6.0v pd8 v il input low voltage v ss 0.15v dd v pd9 v ih input high voltage 0.85v dd 5.0 v dd v note 1: device must be verified at minimum and maximum operating voltages specified in the data sheet. table 4-1: ac characteristics (ta = +10 c to +40 c, v dd = 5.0v 5%) (25 c is recommended parameter no. symbol characteristics min typ max units conditions p1 t r mclr rise time 0.15 1.0 8 m s p2 t f mclr fall time 0.5 2.0 8 m s p3 t ps program mode setup time 1.0 m s p4 t acc data access time 250 ns p5 t ds data setup time 1.0 m s p6 t dh data hold time 1.0 m s p7 t oe output enable time 0 100 ns p8 t oz output disable time 0 100 ns p9 t pw programming pulse width 10.0 100 m s p10 t pwf programming pulse width 10,000 m s configuration word only p11 t rc recovery time 10.0 m s p12 f osc frequency on osc1 dc 5 mhz for incrementing of the pc
pic16c5xx ds30190h-page 14 ? 1999 microchip technology inc. figure 4-1: programming and verify timing waveform figure 4-2: speed verify timing waveform mclr /v pp t0cki osc1 data (rb7:0, ra3:0) (internal) pc 0xfff 0x000 0x001 data in (config) p1 v hh 1/v hh 2 p11 p4 p5 p6 p7 p2 (pc pointing to configuration word) data out (config) data out (config) data in (loc 0x000) p3 p10 p9 p4 p4 p4 p8 p7 p7 p7 p8 p5 p6 p8 p8 data out (loc 0x000) data out (loc0x000) mclr /v pp t0cki osc1 data (rb7:0, ra3:0) pc (internal) data out (config) data out (0x000) 0xfff 0x000 0x001 0x002 0x003 p7 p4 p8 data out (0x001) data out (0x002) data out (0x003) v hh 1 '1'
? 1999 microchip technology inc. ds30190h-page 15 pic16c5xx notes:
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or oth e r intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. in the u.s.a. and other countries. all rights reserved. al l other trademarks mentioned herein are the property of their respective companies. ds30190h-page 16 ? 1999 microchip technology inc. all rights reserved. ? 1999 microchip technology incorporated. printed in the usa. 11/99 printed on recycled paper. americas corporate office microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-786-7200 fax: 480-786-7277 technical support: 480-786-7627 web address: http://www.microchip.com atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770-640-0034 fax: 770-640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508-480-9990 fax: 508-480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 630-285-0071 fax: 630-285-0075 dallas microchip technology inc. 4570 westgrove drive, suite 160 addison, tx 75248 tel: 972-818-7423 fax: 972-818-2924 dayton microchip technology inc. two prestige place, suite 150 miamisburg, oh 45342 tel: 937-291-1654 fax: 937-291-9175 detroit microchip technology inc. tri-atria office building 32255 northwestern highway, suite 190 farmington hills, mi 48334 tel: 248-538-2250 fax: 248-538-2260 los angeles microchip technology inc. 18201 von karman, suite 1090 irvine, ca 92612 tel: 949-263-1888 fax: 949-263-1338 new york microchip technology inc. 150 motor parkway, suite 202 hauppauge, ny 11788 tel: 613-273-5305 fax: 613-273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408-436-7950 fax: 408-436-7955 americas (continued) toronto microchip technology inc. 5925 airport road, suite 200 mississauga, ontario l4v 1w1, canada tel: 905-405-6279 fax: 905-405-6253 asia/pacific hong kong microchip asia pacific unit 2101, tower 2 metroplaza 223 hing fong road kwai fong, n.t., hong kong tel: 852-2-401-1200 fax: 852-2-401-3431 beijing microchip technology, beijing unit 915, 6 chaoyangmen bei dajie dong erhuan road, dongcheng district new china hong kong manhattan building beijing 100027 prc tel: 86-10-85282100 fax: 86-10-85282104 india microchip technology inc. india liaison office no. 6, legacy, convent road bangalore 560 025, india tel: 91-80-229-0061 fax: 91-80-229-0062 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shinyokohama kohoku-ku, yokohama-shi kanagawa 222-0033 japan tel: 81-45-471- 6166 fax: 81-45-471-6122 korea microchip technology korea 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku seoul, korea tel: 82-2-554-7200 fax: 82-2-558-5934 shanghai microchip technology rm 406 shanghai golden bridge bldg. 2077 yanan road west, hong qiao district shanghai, prc 200335 tel: 86-21-6275-5700 fax: 86 21-6275-5060 asia/pacific (continued) singapore microchip technology singapore pte ltd. 200 middle road #07-02 prime centre singapore 188980 tel: 65-334-8870 fax: 65-334-8850 taiwan, r.o.c microchip technology taiwan 10f-1c 207 tung hua north road ta i p e i , ta i wa n , ro c tel: 886-2-2717-7175 fax: 886-2-2545-0139 europe united kingdom arizona microchip technology ltd. 505 eskdale road winnersh triangle wokingham berkshire, england rg41 5tu tel: 44 118 921 5858 fax: 44-118 921-5835 denmark microchip technology denmark aps regus business centre lautrup hoj 1-3 ballerup dk-2750 denmark tel: 45 4420 9895 fax: 45 4420 9910 france arizona microchip technology sarl parc dactivite du moulin de massy 43 rue du saule trapu batiment a - ler etage 91300 massy, france tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 mnchen, germany tel: 49-89-627-144 0 fax: 49-89-627-144-44 italy arizona microchip technology srl centro direzionale colleoni palazzo taurus 1 v. le colleoni 1 20041 agrate brianza milan, italy tel: 39-039-65791-1 fax: 39-039-6899883 11/15/99 w orldwide s ales and s ervice microchip received qs-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona in july 1999. the companys quality system processes and procedures are qs-9000 compliant for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms and microperipheral products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001 certified.

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